“The U.S. could rally together allies that can manufacture GAA structures to stop them from producing for Chinese semiconductor design companies,” said Brady Wang, associate director at research firm Counterpoint.
Samsung will start using the GAA transistor architecture for its 3nm process in 2022, according to the company’s website, while TSMC, the world’s largest contract chipmaker, has a variant of GAA listed in its technology roadmap for its 2nm-grade N2 process.
Despite these limitations, Chinese companies are researching ways to develop EDA software for GAA transistors as part of a national effort to replace foreign technology with domestic solutions, even if performance still lags.
The National EDA Technology Innovation Center, a state-run research institute established last June in Nanjing, capital of eastern China’s Jiangsu Province, has added design tools for GAA structures to the center’s technology roadmap, according to slides the organization showed at Semiconductor World Congress 2024 in Nanjing last week.
In addition to restrictions on design software, China has also been barred from importing extreme ultraviolet (EUV) lithography systems, which are typically required for manufacturing processes at the 7nm node and below, since 2019. Currently, only three chipmakers – TSMC, Samsung and Intel – use ASML’s EUV systems in mass production.
HBM remains under scrutiny in Washington, though there is currently no blanket ban on China, but a separate Commerce Department document released in October said that when China or other countries of concern order silicon wafers overseas, warnings would be issued to foreign foundries, exporters and other entities if the designs include more than 50 billion transistors and HBM chips.
HBM employs 3D stacking, vertically integrating layers of dynamic random access memory chips using technologies such as CoWos, a wafer-level multi-chip packaging technique invented by TSMC.
“Advanced packaging technology itself has proven very challenging for mature companies outside of China,” Nicholas Godois, head of technology research in Asia Pacific at UBS, said during a recent webinar. “You absolutely need cutting-edge development process technology on the front end as well. [chipmaking]That doesn’t exist in China.”
Taiwan-based market research firm TrendForce, in response to questions from The Washington Post, said that China does not currently have the capability to design chips using the GAA architecture, but that mainland packaging and assembly companies such as SJ Semiconductor and JCET have the capability to do 2.5D CoWos.
Randy Abrams, head of Taiwan research at UBS, said it was unclear whether the new regulations would restrict chips for consumer smartphones, but as an alternative to GAA, Chinese design companies could use existing FinFET architecture that works down to 3nm and increase the die size of each chip to close the performance gap.
